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Toward a Faster Screening of Faulty Digital Chips via Current-Bound Estimation Based on Device Size and Threshold Voltage

机译：基于器件尺寸和阈值电压的电流限制估计快速筛选故障数字芯片

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Ching-Hwa Cheng;
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年度 2016
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1. Toward a Faster Screening of Faulty Digital Chips via Current-Bound Estimation Based on Device Size and Threshold Voltage [J] . Ching-Hwa Cheng Journal of Low Power Electronics and Applications . 2016,第2期

机译：通过基于器件尺寸和阈值电压的电流限制估计来更快地筛选故障数字芯片
2. Proton tolerance of multiple-threshold voltage and multiple-breakdown voltage CMOS device design points in a 0.18 /spl mu/m system-on-a-chip CMOS technology [J] . Ying Li, Cressler J.D., Yuan Lu, IEEE Transactions on Nuclear Science . 2003,第6期

机译：采用0.18 / spl mu / m片上系统CMOS技术的多阈值电压和多击穿电压CMOS器件设计点的质子公差
3. Fast high-throughput screening of glutathione S-transferase polymorphism by voltage programming-based multi-channel microchip electrophoresis [J] . Yucheng Sun, Su-Kang Kim, Seong Ho Kang Journal of chromatography, B. Analytical technologies in the biomedical and life sciences . 2018,第期

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4. Comparative analysis of mobility and dopant number fluctuations based models for the threshold voltage fluctuations estimation in 45 nm channel length MOSFET devices in the presence of random traps and random dopants [C] . Ashraf, Nabil, Vasileska, Dragica, Wirth, Gilson, Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on . 2011

机译：基于迁移率和掺杂物数量波动的模型的比较分析，用于在存在随机陷阱和随机掺杂物的情况下估算45 nm沟道长度MOSFET器件中的阈值电压波动
5. Threshold voltage instability on nitride based localized charge trap non-volatile memory devices. [D] . Chuan, Lee Meng. 2015

机译：基于氮化物的局部电荷陷阱非易失性存储器件的阈值电压不稳定性。
6. Model Development for Threshold Voltage Stability Dependent on High Temperature Operations in Wide-Bandgap GaN-Based HEMT Power Devices [O] . Huolin Huang, Feiyu Li, Zhonghao Sun, 2018

机译：宽带隙GaN基HEMT功率器件中取决于高温操作的阈值电压稳定性的模型开发
7. A single device based Voltage Step Stress (VSS) Technique for fast reliability screening [O] . Ji, Z, Zhang, JF, Zhang, WEI, 2014

机译：基于单个器件的电压阶跃应力（VSS）技术用于快速可靠性筛选
8. Fast On-Chip Delay Estimation for Cell-Based Emitter Coupled Logic [R] . O'Brien, P. R., Wyatt, J. L., Savarino, T. L., 1988

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Toward a Faster Screening of Faulty Digital Chips via Current-Bound Estimation Based on Device Size and Threshold Voltage

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